From: jim@n5ial.mythical.com (Jim Graham) Subject: Re: 16550A FIFO IRQ setting question and ideas Date: Sun, 4 Jul 1993 13:23:32 GMT
In article <creed-020793111505@kip-6.taligent.com> creed@taligent.com
(Creed Erickson) writes:
>In article <1993Jul1.025919.890@n5ial.mythical.com>, jim@n5ial.mythical.com
>(Jim Graham) wrote:
>> The idea
>> here is that the software will then receive *ALL* of the characters that
>> are waiting in one interrupt cycle, thus reducing the amount of overhead
>> used in context switching.
>>
>Please allow me to correct/clarify on a fine, but important, point here:
>The 16550 FIFO can do nothing to reduce the context switching overhead,
>that's a run-time constant. What does happen is the number of interrupts,
>and hence the number of trips into the kernal, are reduced with
>consequential reduction of overall system load.
Just to clarify things a bit---this is exactly what I meant. I'll have to
word that better next time to avoid confusion. I was only thinking about
the *OVERALL* performance (after all, as you say, the context switching
overhead *PER INTERRUPT* is beyond the reach of the UART...the only thing
it can do is reduce the number of interrupts and thus reduce the *TOTAL*
amount of context switching overhead).
Btw, thanks for the suggestion---consider that reworded next time. Later,
--jim