From: adrie@ica.philips.nl (Adrie Koolen) Subject: Re: More on the DMA timing problem Date: Wed, 11 Aug 1993 11:19:31 GMT
In article <jmonroyCBKrE9.76n@netcom.com> jmonroy@netcom.com (Jesus Monroy Jr) writes:
>>> The scenario is possible under some conditions and eminently plausible, but
>>> the timings involved on PC hardware at low transfer rates mean that it
>>> will not happen on these machines unless:
>>> 1) some DMA device is seizing the bus for extended burst mode transfers
>>> or
>>>
> The RAM refresh is a burst mode operation.
This makes me dig deep into my memory. As far as I can remember, memory
refresh on a 808[68] PC was done one cycle at a time, controlled by one
timer (which of course was set to some 16us). The DMA channel may have
been programmed to operate in burst mode, but each burst would be only
one cycle and so wouldn't take the CPU bus too long.
Adrie Koolen (adrie@ica.philips.nl)
Philips Consumer Electronics, Eindhoven, the Netherlands