From: jmonroy@netcom.com (Jesus Monroy Jr) Subject: Need Help: problem with DMA on i386 pc Date: Sat, 7 Aug 1993 02:56:27 GMT
mail wjolitz@cardio.ucsf.edu
trail of different DMA modes.
Bill I posted this today on comp.os.386bsd.development
and others.
08-06-1993 jmonroy@netcom.com -
In discussion, the Intel 8237 running on an i386 pc clone with
an ISA bus.
Problem: The FDC driver losses about 1 in every 500 requests
due to a reported "DMA transfer lost". Or about
5-10 DMA data over-runs with a transfer of about
1 megabyte. The data over-runs were reported
as part of the "results" in a DMA transfer involving
the FDC. It seemed to have no consistent behavior.
Conclusion: On DMA channel 0 (zero) the PC is the RAM refresh
which is hardware controlled and has priority over
the FDC, on channel 2. As a consequence, the FDC
is doomed to fail as described.
There seems to be no solution. I am open to any
suggestions. Here is a summary of the activities
to date. Any suggestions appreciated.
1) Added "DMA disable controller" to command string
in an attempt to stop DMA OverRun Problem for the FDC.
(didn't work)
2) Tried Compressed timing and Rotating priority together
and seperately, no luck.
3) Tried DMA_MoDe_BLOCK, alone, only got DMA overrun error
with no data trasnfered.
4) Tried DMA_MoDe_DEMAND, alone, seemed to work the same as
DMA_MoDe_SINGLE; That is the same amount of error ratio.
5) As a last effort before trying odd combinations and the
such I decided to read the DMA status register when the
FDC reported an error. The DMA status returned was
0xb4 indicating:
DMA status register
-------------------
in request | Terminal count reached
---------------------------------
| 3 | 2 | 1 | 0 | 3 | 2 | 1 | 0 |
---------------------------------
8 2 1 4
The above drawing is for my benefit.
As seen above, the DMA completed, but maybe it started
late. Giving the reason for the failure. And what we see is
results. I have no way of telling what happen exactly.
6) After finding this I unmasked the channel in
isa_dmadone(),no luck again.
7) Then added splxxx() around all isa_dmaxxx() calls,
the fdc still reports overruns.
8) Moved the line that "unmask channel" from the bottom
of command string, in isa_dmastart(), to right
after disable_controller command, no change.
9) Tried priming all channels as Intel suggest in the data
guide. By priming, each channel was set to Single
Transfer Mode and Read (the memory), then the channel
was "unmasked". I did this in the fdstart routine.
It only seemed to make matters worse. I went from
0xb4 to 0xbf, 0xbe, 0xb1.
My only resort seems to be to retry.
Does anyone have any other Ideas???
Mail or chain to this posting is fine.
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Jesus Monroy Jr jmonroy@netcom.com
/386BSD/device-drivers /fd /qic /clock /documentation
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