From: dbarker@spang.Camosun.BC.CA (Deryk Barker) Subject: Re: WP-PCF, Linux, RISC? Date: Wed, 21 Apr 1993 00:48:22 GMT
leebr@ecf.toronto.edu (LEE BRIAN) writes:
: In article <1qu8ud$2hd@sunb.ocs.mq.edu.au> eugene@mpce.mq.edu.au writes:
: >In article <C5o1yq.M34@csie.nctu.edu.tw> ghhwang@csie.nctu.edu.tw (ghhwang) writes:
: >>
: >>Dear friend,
: >> The RISC means "reduced instruction set computer". The RISC usually has
: >>small instruction set so as to reduce the circuit complex and can increase
: >>the clock rate to have a high performance. You can read some books about
: >>computer architecture for more information about RISC.
: >
: >hmm... not that I am an authority on RISC ;-) but I clearly remember
: >reading that the instruction set on RISC CPUs is rather large.
: >The difference is in addressing modes - RISC instruction sets are not
: >as orthogonal is CISC.
The original RISCs had small instruction sets, and simple ones. The
idea was that a) every instruction should be completable in a single
clock cycle and b) to have no microcode and c) extensive pipelines.
A few comparisons (from Patterson: Reduced Instruction set computers.
CACM V28. 1, 1985):
CPU Year Instructions Microcode
--- ---- ------------ ---------
IBM 370/168 1973 208 420Kb
DEC VAX 11/780 1978 303 480Kb
IBM 801 1980 120 0
UCB RISC 1 1982 39 0
Stanford MIPS 1983 55 0
While researching for the VLSI VAX, DEC discovered that 60% of the VAX
microcode is there to support 20% of the instruction set which
accounted for a mere 0.2% of all instructions executed. The uVAX 32
subsetted the architecture onto a single chip and used a software
emulator for these very complex instructions, the full VLSI uVAX
included the entire instruction set, was 5-10 times more copmlex but
only ranm 20% faster.
CPU Chips Microcode Transistors
--- ----- --------- -----------
uVAX 32 2 64K 101K
VLSI uVAX 9 480K 1250K